1. Field of the Invention
The present invention relates generally to the fabrication of semiconductor integrated circuits and, more particularly, to a method for fabricating a probing pad of an integrated circuit chip.
2. Description of the Prior Art
In the manufacturing process of integrated circuits (ICs) and chips, a testing operation is a commonly used step. Each IC, whether the IC is in the wafer scale or in the packaging state, has to be tested through a standard testing procedure to ensure functions of each circuit of the IC. Generally speaking, accuracy and speed of a testing procedure are required because of two main concerns: new design of ICs and yield. As IC design progresses the ICs have more functions, and the inner circuits of the ICs become more complicated. Therefore, the accuracy of the testing procedure also becomes more essential.
The testing procedure of testing a single die of a wafer in the above-mentioned wafer scale is also called wafer probing. As known by those skilled in the art, wafer probing is an essential test in IC manufacturing, and it is mainly used to detect device characteristics of each die on the wafer by establishing a temporary electronic contact between an external testing device and the dies on the wafer. Therefore, the produced ICs that conform to the needed specification are selected from the whole wafer before all dies are separated and packaged. Furthermore, the yield of the wafer can be determined through the wafer probing. Therefore, engineers could know the problems of wafer manufacturing by analyzing the yield. In other words, if the yield is a high percentage, this means that the manufacturing procedure is correct, otherwise, if the yield is a low percentage, this means that some problems may have occurred in the manufacturing procedure and some steps of the manufacturing procedure need to be examined again.
FIG. 1 is a cross-sectional, schematic diagram illustrating a transition state during the probing process utilizing a probe tip 30 according to the prior art method. As shown in FIG. 1, a metal layer 14 is formed in a base layer 12 of the chip 10. The metal layer 14 is initially covered by a passivation layer 24. An etching process is then implemented to form a via opening 28 exposing a portion of the underlying metal layer 14. After the formation of the via opening 28, an aluminum pad 16 is formed on the metal pad 14. The probe tip 30 is moved down to touch the aluminum pad 16 through the via opening 28. To ensure good contact between the probe tip 30 and the aluminum pad 16, the probe tip 30 laterally moves a short distance on the surface of the pad 16. This action often results in an uplifted probe mark 36.
When the interconnection of the IC chip employs a copper system and uses low-k materials as insulation layers, the aforesaid probing process directly performed on the aluminum pad 16 may result in exposed copper portion 38 on the metal layer 14 or cracking in the insulation layer due to overly large probing force. It is disadvantageous to expose the underlying copper metal layer 14 because the exposed copper may be oxidized thus damages the chip.